This paper presents a hardware/software co-design method for the implementation of multi-format audio decoder with ultra low power, small chip size, and high flexibility which are most critical factors in embedded devices. This approach can provide both flexibility and low power with high performance in such a way that hardware implementation has been focused on the commonly used critical blocks of multiple audio decoders having intensive computations. Hardware blocks are well modularized to allow easy and rapid architecture exploration of several digital audio standards. The proposed system can decode MP3 bitstream using only about 4MHz clock frequency and AAC bitstream using only about 7MHz clock frequency on average at the sampling rate of 48 kHz and the target bitrate of 128kbps/stereo.
(See document for exact affiliation information.)
https://aes2.org/publications/elibrary-page/?id=14479
(261KB)
Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member Join the AES. If you need to check your member status, login to the Member Portal.
