An efficient method to linearize the switching (power) stage of open-loop class D amplifiers is presented. This technique has been successfully applied to an open-loop fully-digital PWM class D amplifier designed in a 40 nm CMOS process leading to nearly 15 dB improvement in the Total Harmonic Distortion (THD). Simulated open-loop class D amplifier performance resulted to 105 dBA Signal-to-Noise Ratio (SNR), and 1W output power over 8 Ohm with 90% power efficiency and 0.014% THD.
(See document for exact affiliation information.)
https://aes2.org/publications/elibrary-page/?id=18183
(657KB)
Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member Join the AES. If you need to check your member status, login to the Member Portal.
