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For over 15 years, Analog Devices has continued improving its graphical programming environment to support several, audio specific and general purpose digital signal processors (DSPs). As of 2016, all supported processors have either contained single or dual DSP cores whereas both of them have had the same architecture. With the need to have a heterogeneous DSP architecture the team had the challenge to program both cores within the same environment. This paper describes challenges, trade-offs and design decisions made when programming a new heterogeneous DSP core architecture.
Author (s): Chavez, Miguel
Affiliation:
Analog Devices, Wilmington, MA, USA
(See document for exact affiliation information.)
AES Convention: 144
Paper Number:423
Publication Date:
2018-05-06
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Session subject:
Signal Processing/Audio Effects & Instrumentation/Measurements/Forensics
Permalink: https://aes2.org/publications/elibrary-page/?id=19536
(551KB)
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Chavez, Miguel; 2018; Graphical Development Design for a Heterogeneous DSP Core Architecture [PDF]; Analog Devices, Wilmington, MA, USA; Paper 423; Available from: https://aes2.org/publications/elibrary-page/?id=19536
Chavez, Miguel; Graphical Development Design for a Heterogeneous DSP Core Architecture [PDF]; Analog Devices, Wilmington, MA, USA; Paper 423; 2018 Available: https://aes2.org/publications/elibrary-page/?id=19536