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A high-performance jitter-reduction circuit based on high-order phase-locked-loop technique has been built for digital audio. It provides over 40-dB attenuation for midfrequencies but still maintains over 10-Hz cutoff frequency. By employing a crystal-based voltage-controlled oscillator, very low intrinsic jitter is achieved.
Author (s): Wong, Wai-Ki
Affiliation:
City Polytechnic of Hong Kong, Hong Kong
(See document for exact affiliation information.)
AES Convention: 97
Paper Number:3888
Publication Date:
1994-11-06
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Session subject:
Analog Signal Processing
Permalink: https://aes2.org/publications/elibrary-page/?id=6344
(862KB)
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Wong, Wai-Ki; 1994; High-Performance Jitter-Reduction Circuit for Digital Audio [PDF]; City Polytechnic of Hong Kong, Hong Kong; Paper 3888; Available from: https://aes2.org/publications/elibrary-page/?id=6344
Wong, Wai-Ki; High-Performance Jitter-Reduction Circuit for Digital Audio [PDF]; City Polytechnic of Hong Kong, Hong Kong; Paper 3888; 1994 Available: https://aes2.org/publications/elibrary-page/?id=6344