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This paper describes a new digital signal processor (DSP) LSI for a digital audio tape (DAT) recorder with a fully digital phase locked loop (PLL). In our newest DSP which uses a ring oscillator to lower the master clock frequency, we have improved the PLL`s master to playback (PB) clock frequency ratio to 2.6, where in our currently available DSP, PLL`s master to PB ratio is 5.2.
Author (s): Fukuda, Shinichi; Fukami, Tadashi; Moroboshi, Arihiro
Affiliation:
Sony Corporation, Tokyo, Japan
(See document for exact affiliation information.)
AES Convention: 93
Paper Number:3373
Publication Date:
1992-10-06
Import into BibTeX
Session subject:
Digital Innovations in Audio Technology
Permalink: https://aes2.org/publications/elibrary-page/?id=6760
(568KB)
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Fukuda, Shinichi; Fukami, Tadashi; Moroboshi, Arihiro; 1992; New Digital PLL for 8-10 Modulation Code Used by DAT [PDF]; Sony Corporation, Tokyo, Japan; Paper 3373; Available from: https://aes2.org/publications/elibrary-page/?id=6760
Fukuda, Shinichi; Fukami, Tadashi; Moroboshi, Arihiro; New Digital PLL for 8-10 Modulation Code Used by DAT [PDF]; Sony Corporation, Tokyo, Japan; Paper 3373; 1992 Available: https://aes2.org/publications/elibrary-page/?id=6760