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This paper examines desirable DSP architectural features to consider for implementation of real time audio applications using a 32-bit Single Instruction Multiple Data (SIMD) DSP based on a Modified Harvard Architecture. This discussion will examine the specific features in this architecture that are desirable for implementing many of today`s professional and consumer audio equipment. The first topic covered are the important audio processor-specific characteristics of this SIMD architecture such as data word size, dynamic range/SNR capabilities, memory organization, processor speed, benchmarks and I/0 capabilities. Part Two will highlight a couple of example DSP audio algorithms to demonstrate the benefits of such an architecture which can speed up DSP execution by as much as a factor of 5 over earlier SISD SHARC: architectures.
Author (s): Tomarakos, John; Duggan, Colin; Steyerl, Stefan
Affiliation:
Analog Devices, Norwood, USA
(See document for exact affiliation information.)
AES Convention: 106
Paper Number:4983
Publication Date:
1999-05-06
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Session subject:
Signal Processing
Permalink: https://aes2.org/publications/elibrary-page/?id=8197
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Tomarakos, John; Duggan, Colin; Steyerl, Stefan; 1999; 32-Bit SIMD SHARC Architecture for Digital Audio Signal Processing Applications [PDF]; Analog Devices, Norwood, USA; Paper 4983; Available from: https://aes2.org/publications/elibrary-page/?id=8197
Tomarakos, John; Duggan, Colin; Steyerl, Stefan; 32-Bit SIMD SHARC Architecture for Digital Audio Signal Processing Applications [PDF]; Analog Devices, Norwood, USA; Paper 4983; 1999 Available: https://aes2.org/publications/elibrary-page/?id=8197